TTTC's Electronic Broadcasting Service

IEEE Transactions on Emerging Topics in Computing

Special Issue/Section on Reliability-aware Design and Analysis Methods for Digital Systems: from Gate to System Level

DEADLINE EXTENDED TO MARCH 16th, 2017

CALL FOR PAPERS

Scope

The continuous scaling of CMOS devices as well as the increased interest in the use of emerging technologies make more and more important the topics related to defect and fault tolerance in digital systems. To address the increasing complexity of digital systems and their challenging reliability requirements, it is imperative to employ design and analysis methods to different levels of the abstraction, starting from the system level down to the gate level. The IEEE Transaction on Emerging Topics in Computing (TETC) seeks original manuscripts for a Special Section on Reliability-aware Design and Analysis Methods for Digital Systems: from Gate to System Level scheduled to appear in the March issue of 2018. All aspects of design, manufacturing, test and analysis of systems affected by defects during manufacturing and by faults during system operation are of interest. 

The topics of interest for this special issue include, but are not limited to:

  1. Yield Analysis and Modeling Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
  2. Design For Testability in IC Design FPGA, SoC, NoC, ASIC, microprocessors.
  3. Error Detection, Correction, and Recovery Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques, architectural-specific techniques, system-level strategies.
  4. Dependability Analysis and Validation Fault injection techniques and environments; dependability characterization; aging modeling and analysis.
  5. Repair, Restructuring and Reconfiguration Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
  6. Defect and Fault Tolerance Reliable circuit/system synthesis; radiation hardened and/or tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors; aging management and recovery strategies.
  7. Fail-Safe Design for Critical Applications Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
  8. Reliable Systems Designed with Emerging Technologies Design techniques for the system composed of CNTs, QCA, DNA, RTDs, SETs, and molecular devices.
  9. Design for Security Fault attacks, fault tolerance-based counter-measures, Scan-based attacks and countermeasures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and reliability.

Guide for authors

TSubmitted articles must not have been previously published or currently submitted for journal publication elsewhere. An extended version of an article appearing in the conference proceedings (and in particular, IEEE DFT 2016) can be submitted provided that it has substantially new content w.r.t. to the original conference version. The conference paper must be cited in the main text and the cover letter must clearly describe the differences with the conference version and clearly identify the new contributions. As an author, you are responsible for understanding and adhering to the submission guidelines. You can access them at the IEEE Computer Society web site, www.computer.org. Please thoroughly read these before submitting your manuscript. Please submit your paper to Manuscript Central at https://mc.manuscriptcentral.com/tetc-cs.

Key Dates

  • Submission deadline: March 16, 2017.
  • Reviews completed: June 1, 2017.
  • Major revision due (if needed): July 1, 2017.
  • Reviews of revisions: August 1, 2017.
  • Minor revision due (if needed): September 1, 2017.
  • Final notification of acceptance/rejection: November 1, 2017.
  • Publication material for final manuscripts due: December 1, 2017.
  • Special section publication: First issue of 2018.
Guest editors
  • Qiaoyan Yu (University of New Hampshire) – qiaoyan.yu@unh.edu
  • Antonio Miele (Politecnico di Milano) – antonio.miele@polimi.it
  • Omer Khan (University of Connecticut - khan@uconn.edu)
  • Maria K. Michael (University of Cyprus - mmichael@ucy.ac.cy


The special issue is supported by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR
Michael Purtell
Intersil
- USA
Tel. +1-408-372-6015
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR

Synopsys, Inc.
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC
André IVANOV
U. of British Columbia - Canada
Tel. +1
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel.+81-743-72-5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com


This message contains public information only. You are invited to copy and distribute it further.

For more information contact the TTTC office or visit http://tab.computer.org/tttc/

To remove or modify your contact information, or to register new users, please click here and follow the on-line instructions.